The present disclosure relates generally to a delay locked chain. More particularly, the present disclosure relates to a high resolution and/or low power delay chain.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In electronics, a signal is used to convey information. A delay chain is a digital circuit that may be used to change a phase (a position of a point of time) of the signal. The delay chain may be implemented as a closed loop, such as in the case of a delay-locked loop. The signal may be a clock signal that includes a periodic waveform that may be used to coordinate actions of digital circuits. The clock signal oscillates between a high state and a low state. Digital circuits using the clock signal may become active at a rising edge and/or a falling edge of the clock cycle. The delay chain may be used to position or delay a signal. For example, the delay chain may position or delay the signal relative to an incoming signal. In particular, the delay-locked loop may match phases between an input clock signal and a feedback clock signal by delaying the input clock signal such that the delayed input clock signal is in phase with the feedback clock signal. The delay that is added to the input clock signal by the delay-locked loop may include two components: a coarse delay component and a fine delay component.
The coarse delay component may be generated by selecting one or more delay cells among a chain of complementary metal-oxide-semiconductor (CMOS) inverters (or buffers). Each delay cell may include a first CMOS inverter that buffers and inverts the polarity of the input clock signal (such that the inverted input clock signal is 180 degrees out of phase with the original input clock signal), and an immediately adjacent second CMOS inverter further buffers and re-inverts the input clock signal (such that the re-inverted input clock signal is in phase with the original input clock signal). As such, the smallest incremental delay (e.g., phase or delay resolution) achievable by the coarse delay component is that generated by two back-to-back inverters. Because the CMOS inverter delay in deep sub-micron process (e.g., less than 0.1 micrometer or micron) may typically be less than 50 picoseconds (ps), the minimum phase resolution of the coarse delay component may be about 100 ps.
By contrast, the fine delay component may be generated by selecting one or more interpolator cells of a phase interpolator, such as a digital interpolator. The interpolator interpolates between two incoming signals (e.g., from a first delay cell and an immediately adjacent second delay cell associated with the coarse delay component). The fine delay component is a delay amount less than the minimum phase resolution of the coarse delay component and is added to the coarse delay component to achieve greater phase resolution than can be achieved by the coarse delay component alone. The resolution of the fine delay component is dependent on the number of bits of the interpolator. In particular, the resolution of the fine delay component doubles for each added bit of the interpolator. However, adding a bit to the interpolator approximately doubles both the size of and the power consumed by the delay-locked loop.